copyright © 2007-2022 Edwin E Klingman
all rights reserved
| PAT. NO. | Title of Patent | |
|---|---|---|
| 34 | 11,313,873 | Velocity measuring device |
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Disclosed herein is a velocity measuring device to be used in a moving frame to determine the velocity of the moving frame. At least one beam of light is emitted from a site in the moving frame and travels to a mirror disposed in the moving frame and back to the site at which the emission occurred, after which the beam is detected by a detector. By measuring the round trip time of the light beam from emission to detection, a factor gamma can be determined from which the velocity of the moving frame can be computed.
Filed: December 17, 2020 Issued: Apr 26, 2022 cited by: 0 | ||
| 33 | 7,984,442 | iMEM Intelligent memory device multilevel ASCII interpreter |
|
System and method for interpreting ASCII code fetched from a code space of a task partition that is part of memory shared by a host processor and a multitask controller (MTC). The MTC includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The shared memory also includes a system partition containing a code space. The fetched code is monitored for adjacent ASCII alphabetic characters and if at least two are found and the fetched code is terminated by an ASCII space character, the code table in the code space of the system partition is scanned to find a command that matches the fetched code. The byte in the table immediately following the matched fetched code and having a bit set indicating that it is interpreted is obtained and written over the ASCII space character in the code space of the task partition.
Filed: December 23, 2004 Issued: July 19, 2011 cited by: 0 | ||
| 32 | 7,856,632 | iMEM ASCII architecture for executing system operators and processing data operators |
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A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The computing system operates on ASCII instructions which includes a set of ASCII operators. The operators include both ASCII data operators and ASCII system operators. The system operators include characters for specifying a request to obtain resources, to perform a task switch, to perform a task suspension, to execute a branch, to transfer results of an operation into a task data register, to transfer data into a processing element, to record the current location of instruction execution in the task code space, to treat a sequence of symbols as a group, and to perform an output function. Data operators include characters for specifying a request to perform arithmetic and logical operations on data.
Filed: January 27, 2005 Issued: December 21, 2010 cited by: 1 | ||
| 31 | 7,823,161 | iMEM Intelligent memory device with variable size task architecture |
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A variable task size architecture is disclosed. A system partition is included that is dedicated to system use. The system partition contains a number of specifiers that describe the number of tasks in the system memory, and for each task partition, the location and size of a task status register, the number, location and size of each of a set of task data registers, and the size and starting location of task code. Specifiers include the word size in bytes, the number of words per increment, the number of increments per partition, the number of increments per data register, and the number of data registers. In one embodiment, the number of tasks is available from an input port. The task specifiers and the number of tasks are accessible to the scheduler unit via the data flow unit when a reset signal is released.
Filed: November 1, 2004 Issued: October 26, 2010 cited by: 0 | ||
| 30 | 7,823,159 | iMEM Intelligent memory device clock distribution architecture |
|
A computing system that includes one or more processing elements, a memory connected to a host processor and a multitask controller, where the multitask controller includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The processing elements, the scheduler unit, the data flow unit, the executive unit, and the resource manager unit are each synchronously clocked by a clock signal. The processing elements, multitask controller interface of the memory, the executive unit, and the scheduler unit are each operative to change one or more interface signals on a positive transition of the clock signal while the resource manager unit and dataflow unit are each operative to change one or more interface signals on a negative transition of the clock signal. Because adjacent units are clocked on opposite edges, the speed of transfer of information between the units is improved.
Filed: December 3, 2004 Issued: October 26, 2010 cited by: 0 | ||
| 29 | 7,908,603 | iMEM ASCII FPU architecture |
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A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. One of the processing elements is a floating point element. In one embodiment, the floating point element performs floating point calculations on ASCII data. The floating point element receives data in the form of ASCII character strings that are terminated by an ASCII space character and control information via a strobe that indicates the function to be performed on the data. The functions includes addition, subtraction, multiplication, division, and push and pop. The floating point element performs floating point calculations for a particular task which is indicated by a tag that is stored in the floating point element. Status of a floating point element is available via a read strobe that returns a status byte.
Filed: January 27, 2005 Issued: March 15, 2011 cited by: 1 | ||
| 28 | 7,926,060 | iMEM reconfigurable architecture |
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A computing system that includes a number of processing elements, a memory and a multi-task controller. In one embodiment, the path between the resource manager and the processing elements is the same for all processing elements. In another embodiment, the data path is different between different processing elements. A processing element receives a request via a strobe signal and data on a path between the resource manager and the processing element and reports status on the data path via a different strobe signal. The request to the processing element may specify floating point computations, as well as sorting operations. The processing element can use an auxiliary memory to aid in the sorting operations. Push and pop functions are processed by the processing element to facilitate the loading of multiple data operands in the processing element.
Filed: January 27, 2005 Issued: April 12, 2011 cited by: 0 | ||
| 27 | 7,865,696 | iMEM task index register architecture |
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A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The memory has an interface that includes a task page mechanism with an index register. A portion of the multi-task controller also has a task page register for accessing the memory via another interface. The task page mechanism provides access to the memory by the host processor. The index register can be loaded by either the address or data bus of the host processor. In one embodiment, the task page mechanism includes a comparator and a counter to facilitate a polling scan of the status of the various tasks in the memory.
Filed: January 27, 2005 Issued: January 4, 2011 cited by: 0 | ||
| 26 | 7,926,061 | iMEM ASCII index registers |
|
A computing system that includes a number of processing elements, a memory and a multi-task controller. The memory is organized into a set of logical partitions. Task partitions describe a task and include task state information, task data registers and ASCII task instructions. The task state information includes a set of index registers that are accessible by the task instructions. The index registers typically have dedicated locations in the task partition and are referred to by lower case ASCII alphabetic characters. Index registers are used to refer to a task partition in some cases or to a location in the current task partition in other cases for purposes of branching. Index registers can be incremented or decremented and loaded with an immediate data value. In one embodiment, the data flow unit is used to interpret the branch code and fetch contents of a named index register used in the branch.
Filed: January 27, 2005 Issued: April 12, 2011 cited by: 0 | ||
| 25 | 7,882,504 | iMEM Intelligent memory device with wakeup feature |
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A wakeup mechanism for computing system is disclosed. A wakeup unit connected to a host interface is configured to detect a sequence of data values and to generate the activation signal if the detected sequence matches an expected sequence of data values. First, a read by the host processor at a particular address in memory is detected by the wakeup unit. Next, a sequence of data values is written to the address by the host processor and the wakeup unit compares the sequence to an expected sequence. If there is a match, the wakeup unit causes the multitasking controller to execute a test of the data in memory. If the test is positive, then an indicator is written to the address and when the host reads the indicator, the wakeup unit causes the multitask controller to become active.
Filed: September 30, 2004 Issued: February 1, 2011 cited by: 0 | ||
| 24 | 8,745,631 | iMEM Intelligent memory device with ASCII registers |
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An ASCII-based processing system is disclosed. A memory is divided into a plurality of logical partitions. Each partition has a range of memory addresses and includes information associated with a particular task. Task information includes contents of task state register and one or more task data registers, with each task data register having an ASCII name. Each task data register is successively labeled with a unique alphabetic character label starting with the character `A.` A dataflow unit within the processing system is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task. Task instructions can include ASCII characters that indicate a request for resources and indicate the ASCII-character designated names of task data registers on which the task instruction operates. A processing element receiving the task instruction performs the operation indicated by the ASCII operator code on the indicated task data registers.
Filed: September 9, 2004 Issued: June 3, 2014 cited by: 0 | ||
| 23 | 7,594,232 | Intelligent memory device (iMEM) |
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Coordination between multiple processors presents a set of difficult problems, since most processors are not designed for multi-processing, but for multi-tasking. Additionally, CPUs are increasingly limited by the memory bandwidth bottleneck. The iMEM architecture addresses the multi-processing problem, by simplifying processor access, and the memory bandwidth problem, by distributing intelligence across the memory system. ASCII encoding of task structure and instructions addresses compiler complexities.
Filed: August 4, 2005 Issued: September 22, 2009 cited by: 2 | ||
| 22 | 7,187,662 | A Table Driven Call distribution System for Local and Remote Agents. |
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A table driven call management system for an organization having a plurality of departments and agent. The call management system is capable of supporting local and remote agents each of which can have the same degree of access to the organization's information. Calls are received by the call management system and handled according to a table describing a department in the organization. If an agent for the department is available according to the table, the call is transferred to the agent, either local or remote. If the agent is not available, the call is transferred to another department according to an entry in the table. If no department has an agent available to take the call, a caller message is recording in a department mailbox or a default mail box or the call is transferred to an available operator. Call management software is object oriented having only two objects, a call manager object and an array of call objects, each call object including a department table with which the call is currently associated. The software is flexible so that the department tables can be tailored to the organization and the handling policy can be easily changed. To implement the system only the department tables describing the organization's structure and the voice menus need to be entered into the call management system. The call management system eliminates the need for a separate telephone system for the organization and any private switch. A plurality of computers in the organization can function as a distributed call management system.
Filed: August 31, 1999 Issued: March 6, 2007 cited by: 0 | ||
| 21 | 7,043,568 | Configuration selection for USB device controller |
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A selection system for configuring a device controller. The selection system includes a plurality of state machines each of which has a portion of the configuration information needed to inform a host, connected to the device controller via a serial bus, of the device configuration as well as the configuration, interface and endpoint information. The selection system also includes a selection circuit that selects one of the plurality of state machines in response to a selection code that can be set by a user manually or automatically by programming are register. The manual setting of the selection code is by means of a set of configurable pins which are selected as the default source of the selection code by the selection system.If there are available a variety of device configurations and associated interface and endpoint configurations, the selection system selects one of the device configurations and the associated other configuration information in response to the same selection code, thereby maintaining consistency between the device configuration information and the other associated configuration information.
Filed: September 26, 2000 Issued: May 9, 2006 cited by: 5 | ||
| 20 | 6,976,069 | Multi-site network monitor for measuring performance over an internet |
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An apparatus and method of measuring the performance of a computer network by determining transit times of packets between two selected sites connected by the computer network and the public switched telephone network and deriving from those transit times a measure of the performance of the computer network. Software establishes a network connection and a circuit switched connection between the two selected sites. A pair of messages is sent, at the same or nearly the same time, over the network connection and the circuit-switched connection and the transit time for a one way trip over the network connection is derived from the trips over the network and circuit-switched connections. This furnishes a measurement from which performance statistics of the computer network can be derived.
Filed: January 21, 2000 Issued: December 13, 2005 cited by: 1 | ||
| 19 | 6,928,505 | USB device controller |
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A device controller for connecting a function engine that supports an application to a packet-switched serial bus to which a host device is connected. The interface device includes a serial interface engine for transferring packets between the serial bus and the function engine and an interfacing device that employs a plurality of state machines in a device configuration module. The state machines of the device configuration module operate to configure the interfacing device and make that configuration known to the host. Additionally, for each interface of the function engine that is a group of state machines, at least one of which transfers data between the serial interface engine and the function engine. In one embodiment the serial bus is the USB and the configuration module conforms to the configuration protocol of the USB. As an additional aspect of the invention multiple configurations are supported by the device configuration module. These multiple configurations are user-selectable configurations that can only be changed at configuration time. Once configured the device controller maintains the configurations through out its operation until reset and re-configured. Multiple configurations are provided to minimize the number of different device controllers needed in inventory and to provide a single, flexible device for various controller applications.
Filed: September 26, 2000 Issued: August 9, 2005 cited by: 17 | ||
| 18 | 6,789,212 | Basic cell for N-dimensional self-healing arrays |
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A system is described capable of excising individual cells in an N-dimensional array and healing the array connectivity without manual intervention. Thus cells that fail can be deleted and the array remain viable, although possibly requiring re-synchronization procedures to be performed. The system allows either replacement of bad cells or bypassing of bad cells, with appropriate cost and operational differences. Both level sensitive and edge sensitive excision mechanisms are described and the consequences of each discussed. The invention applies to processor arrays with one cell per physical chip or many cells per chip, and handles uni-directional or bi-directional data flows, and is generally both interface independent and technology independent.
Filed: March 20, 2000 Issued: September 7, 2004 cited by: 22 | ||
| 17 | 6,584,525 | Adaptation of standard microprocessor architectures via an interface to a configurable subsystem |
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A system for extending standard processors using either undefined op-codes or sparse address spaces to maintain the use of legacy processor tools and reduce the complexity of the design process. The disclosure describes a method and apparatus for adding circuitry to processing units that allows partitioning of the design into a fixed processing unit derivative and a configurable subsystem. The legacy processor unit language tools work with the fixed processing unit derivative while the logic design tools work well with the configurable subsystem. In one embodiment, the configurable subsystem is implemented with easily available programmable Logic Devices (PLD's and FPGA's).
Filed: November 19, 1999 Issued: June 24, 2003 cited by: 8 | ||
| 16 | 6,425,122 | Single stepping system and method for tightly coupled processors |
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A method for controlling the execution of a sole target processor or a target processor embedded in a chain of target processor units by a host-processor. The target processor unit includes a shared control register, a shared memory accessible by both the target and host processor and a code memory alterable by the host processor and containing the target processor program. The shared control register includes a single step flag to indicate that the host processor is setting the single step mode of operation for the target processor. The shared control register further includes a clock inhibit flag to permit the target processor to stop execution. Clearing the clock inhibit flag releases the target processor to execute the program in the code memory during which the target processor tests the single step flag to determine whether it should stop execution after one instruction has been executed. If the flag is set the target processor reports its instruction pointer to the host processor via the shared memory and stops.
Filed: June 23, 1999 Issued: July 23, 2002 cited by: 7 | ||
| 15 | 6,219,736 | Universal serial bus (USB) RAM architecture for use with microcomputers via an interface optimized for integrated services device network (ISDN) |
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A RAM-based interrupt-driven interface device is disclosed for establishing a communication link between a universal serial bus (USB) host and a microcontroller device for providing a control function, the interface device being operative to receive digital information in the form of command, data and control packets from the host and to process the packets and communicate the processed digital information to the microcontroller device, and in response thereto, the microcontroller device being operative to communicate digital information to the interface device for processing and transfer thereof to the host. The interface device includes means for receiving a command generated by the host through a USB bus, means for storing the host-generated command and for generating an interface device interrupt signal upon storage of said host-generated command for use by the microcontroller device in responding to the host-generated command, a microcontroller bus for transferring microcontroller information and the interface device interrupt signal between the interface device and the microcontroller device. The interface device further includes means for receiving a microcontroller command from the microcontroller device in response to said interface device interrupt signal and means for storing the microcontroller command and it is operative to generate a microcontroller device interrupt signal upon storage of the microcontroller command for use by the interface device in developing an address for identification of the interface device to the host during subsequent communications therebetween, wherein during communication between the host and the interface device, the interface device-developed address is used by the interface device to identify host-provided information in the form of packets, and upon processing of the host-provided information, to provide the microcontroller device with the necessary information to allow it to respond to the host thereby allowing a generic microcontroller device to be flexibly interfaced with a USB, host for communication therebetween.
Filed: November 12, 1998 Issued: April 17, 2001 cited by: 81 | ||
| 14 | 6,021,453 | Microprocessor unit for use in an indefinitely extensible chain of processors with self-propagation of code and data from the host end, self-determination of chain length and ID, (and with multiple orthogonal channels and coordination ports) |
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A novel architecture is based on a general purpose microcomputer with an "upstream" bus and a "downstream" bus. The upstream bus interfaces to an integrated multiport RAM that is shared between an upstream processor and the local processor, and possesses both upstream and local (downstream) interrupts associated with dedicated locations in RAM. The upstream bus can be operated in two modes, a standard (EISA) PC bus MASTER mode in which the dual port RAM is compatible with an IBM PC bus and a SLAVE mode in which the upstream bus is compatible with the downstream bus. An indefinitely long chain of such processors can be initialized by one host. Orthogonal channels (decoupled from the main upstream/downstream bus) can be used to achieve unique functionality based on host control of arrays of such processors.
Filed: September 9, 1997 Issued: February 1, 2000 cited by: 25 | ||
| 13 | 5,950,172 | Secured electronic rating system |
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A remote communication system for facilitating secure on-line evaluation of goods based upon consumers' satisfaction through electronic media wherein a suitable local user input device in association with a data transmission system, couples the user input to a packet network system for communicating to a remote receiver/decoder apparatus to obtain potentially desired scoring information such as an electronic evaluation form regarding a previously purchased product. Upon selection of scoring option by the user, a telcom network communication link for communicating a telephone number associated with the desired product from the user to the remote receiver allows the user to score the desired product. The telcom connection, linking the user input device to the remote server device may also include a toll-free 800 telephone number system to encourage shoppers to perform evaluations of purchased product without incurring costs associated therewith. During the telcom connection, a buyer identification number may be used to limit rating input to one evaluation per buyer thereby increasing accuracy of product evaluation.
Filed: July 19, 1996 Issued: September 7, 1999 cited by: 172 | ||
| 12 | 5,860,021 | Single chip microcontroller having down-loadable memory organization supporting "shadow" personality, optimized for bi-directional data transfers over a communication channel |
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A microcontroller down-loadable memory organization supporting "shadow" personality, optimized for connecting a computer system to an ISDN network to facilitate transmitting and receiving of data, the microcontroller including a processor and a memory structure having ROM memory space for storing program code therein and further including a dual port RAM for connection between the computer and the processor, the dual port RAM having RAM memory space for storing program code therein and shared RAM for storing data capable of being simultaneously accessible by the processor and the computer, wherein the program ROM and the program RAM are selectively used by the computer to store program code by the computer using a ROM/RAM* select signal, and wherein the starting address in the shared RAM wherein data is stored is selectably offset from the starting address of the code RAM and the code ROM.
Filed: April 24, 1997 Issued: January 12, 1999 cited by: 55 | ||
| 11 | 5,799,285 | Secure system for electronic selling |
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A remote communication system for facilitating secure electronic sales of products, wherein a suitable seller input device in association with a local seller data transmission system couples the seller to a packet network system for communicating to a remote receiver/decoder apparatus to download registration data to the seller system. Upon retrieving a telephone toll number from the remote apparatus, a telcom network communication link for communicating the telephone number from the seller to the remote receiver allows the seller to upload the product that is to be offered for sale to the remote apparatus. The telcom connection, linking the seller system to the remote apparatus may also include a 900 number billing system whereby a fee is assessed and charged at a rate determined by the toll connection provider after uploading the product.
Filed: August 30, 1996 Issued: August 25, 1998 cited by: 348 | ||
| 10 | 5,729,594 |
On-line secured financial transaction system through electronic media
( Prior art used to initiate Amazon One-Click patent re-examination ) |
|
A remote communication system for facilitating secure electronic purchases of goods in on-line, wherein a suitable local user input device in association with a data transmission system, couples the user input into a packet network system for communication to a remote receiver/decoder apparatus to TRY a potentially desired product. Upon selection of the desired product by the user, a telcom network link is used to communicate a telephone number associated with the desired product from the user to the remote receiver to allow the user to BUY the desired product. The telcom network used to link the user input device to the remote apparatus may also include a 900 number billing system for assessing and collecting fees for use of the system.
Filed: June 7, 1996 Issued: March 17, 1998 cited by: 309 | ||
| 9 | 5,721,729 | Universal input call processing system |
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The present invention is directed to an apparatus and method that provides a universal call processing system to process all possible data types transmitted over an ISDN telephone line. A universal call processing system generally comprises an ISDN interface subsystem, a call control subsystem, a call processing subsystem, a controller state machine, and user interface devices.
Filed: January 24, 1996 Issued: February 24, 1998 cited by: 20 | ||
| 8 | 5,680,589 | Ring communication system using ISDN |
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Ring communication system using ISDN including terminal adapter hardware and associated software that can be combined with a general purpose computer and used to provide a work station or party unit which can be linked together with other similarly configured units via the ISDN to provide a closed wide area network. Although the system can be implemented on any type of computer using any programming language, in the preferred embodiment proprietary software designated WinISDN.DLL in a Microsoft Windows.TM. environment is used to implement a novel algorithm in Visual Basic or C-language programming systems. The hardware aspects of the invention are provided in a terminal adapter card that includes a dual port RAM, an ISDN controller, and a subscriber access controller. The adapter card plugs into the (E)ISA bus that is the PC standard bus/backplane.
Filed: June 8, 1995 Issued: October 21, 1997 cited by: 14 | ||
| 7 | 5,541,930 | Byte aligned communication system for transferring data from one memory to another memory over an ISDN |
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A system with source and destination telecommunications transceivers for communicating therebetween over an Integrated Digital Services Network, each having a general purpose computer coupled to an interface circuit for conditioning outgoing and incoming data to and from the communications network. The interface circuit is constructed with a dual port RAM, a subscriber access controller and an ISDN controller. A typical data flow proceeds with the source controller CPU sending bytes of data from a sending buffer in its memory to a first transmit buffer in the dual port RAM. This process continues until the last address in the buffer is filled, whereupon the dual port RAM outputs an interrupt signal to the ISDN controller which responds by sending the data bytes in the buffer to the subscriber access controller for transmission to the ISDN, and sends a control signal instructing the computer to load a second transmit buffer. When the first buffer is emptied the ISDN controller instructs the computer to load the second, etc until all the data is transmitted. When data is being received from the ISDN by the subscriber access controller, it send an interrupt signal to the ISDN controller to hold outgoing data and transfer the incoming data to the computer. The ISDN controller loads the incoming data into one of two receive buffers, and when it is full, sends a signal to the computer to unload the data and proceeds to load the second receive buffer, after which the computer is notified to unload the second buffer. This process is repeated until the incoming data is processed. This process retains byte alignment throughout the interface circuit. In the event that the communications network should require data to be supplied in HDLC frame format, this is provided for by programming in the computer, as is the detection of incoming HDLC framed data and the required extraction of data bytes therefrom.
Filed:Filed: January 10, 1995 Issued: July 30, 1996 cited by: 39 | ||
| 6 | 5,452,301 | Data transmission and control system using local, externally generated D, Q, and M bits in X.25 packets |
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A data transmission and control system using local, externally generated D, Q, M bits in X.25 packets, and including a controller, a controlled device and a transceiver module at each of a plurality of locations. The controller at each location generates and delivers user controlled D, Q and M bits on separate lines and other data on an input/output data bus to the transceiver. The transceiver receives the Q, D, M bits and other data and assembles the data bits with other standard organizational bits to form X.25 information packets according to X.25 protocol. An ISDN interface then inserts the X.25 information packets in standard 48 bit frames for transmission over the ISDN network. The D, Q, M bits and other data are then received at a remote location where the process is reversed, the transceiver receiving the X.25 information packets, extracting the D, Q, M bits and applying them to separate terminals, and extracting the other data and applying it to an input/output data bus, all of which are delivered to a controller. The controller then responds to the D, Q, M bits and other data to act upon the controlled device. The apparatus at any one of the locations can communicate with apparatus at any of the other locations in a similar manner.
Filed:Filed: April 26, 1994 Issued: September 19, 1995 cited by: 3 | ||
| 5 | 5,337,403 | Digital signal processing method and apparatus including a graphic template display |
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A digital signal processing apparatus including a graphic template display including an input circuit for sampling, digitizing and storing successive samples of an input signal, a signal processor for scaling the sampled signal data, a buffer for storing the scaled signals, a copy memory for storing a copy of the scaled signal data, a template memory for storing template data, an image retrieval circuit for accessing and reading out the stored signal and template data, a data mapping circuit for reformatting the stored image data, a display memory for holding the reformatted image data for cyclical display, a memory access circuit for accessing and combining the reformatted image data and the display memory data, and for providing the timing necessary for presentation of the combined data, and display apparatus for displaying the combined data in an original format.
Filed: September 18, 1991 Issued: August 9, 1994 cited by: 16 | ||
| 4 | 5,253,273 | ISDN "S" signal detection and display apparatus |
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A ISDN "S" signal detection and display apparatus including a clock signal generator for synchronizing to the "S signal" and for developing a frame sync clock, a signal converter for connection across the "S" interface to develop a "clean" digital signal corresponding to S-signals received at the "S" interface, a signal processor responsive to the frame sync clock and operative to sample successive S-signals, a storage buffer for temporarily storing the sampled signals, and a display for reporting and/or displaying the averaged signals.
Filed: September 18, 1991 Issued: October 12, 1993 cited by:0 | ||
| 3 | 4,081,669 | Recognition system for class II robots |
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A recognition system for robots is responsive to encoded information from a plurality of sources for enabling a robot to recognize and identify the sources. A receiver located on the robot detects incoming signals and decodes them. The decoded signal is compared with information stored in the robot memory to provide source identification. A direction determining sub-system incorporated into the receiver provides source direction information. The system may utilize either digital or analog techniques.
Filed: February 20, 1976 Issued: March 28, 1978 cited by: 22 | ||
| 2 | 3,938,892 | Electronic Optical Transfer Function Analyzer |
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An electronic optical analyzer for use in systems such as optical transfer function analyzers eliminates mechanical scanning systems and comprises entirely electronic image dissection means for dissecting an image transmitted by an optical system under test and producing an electric output signal representative of the beam intensity at a selected element of the image. The image dissection means is preferably (in the case of visible light) an image dissector tube whose positioning coils serve as an image element addressing means. The system is useable with any optical system including visible light, other electromagnetic radiation or charged particles (ions or electrons) so long as the image dissection means is responsive to the beam in question. The optical system under test must produce a real image at the image dissection surface of the image dissection means in order for readily evaluatable data to be obtained. The entire system is preferably computer controlled in order to obtain the necessary data quickly and accurately and to calculate the optical transfer function of the optical system under test on line. With this system both the modulation transfer function and the phase transfer function may be calculated. The digital computer can control the analyzer in any of several modes such as single scan, multiple scan with averaging of values to improve the signal to noise ratio and pass/fail production testing. output from the computer can be in any of several forms, such as displays on display devices, printouts or process control commands such as accept/reject commands in production testing.
Filed: April 24, 1973 Issued: February 17, 1976 cited by: 10 | ||
| 1 | 3,889,155 | Image Dissector Tube Calibrator |
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The photosensitive screen of an image dissector tube is illuminated with a light pattern having parallel opposite edges, and a sweep signal is applied to the deflection coils of the tube causing scanning of the pattern in a line perpendicular to the edges and generation of an output video pulse. The sweep signal is in the form of a time variable current whose average rate of change during the scan of the line is a constant and dependent on a settable control circuit. Measurement of the output pulse width permits the setting of the slope control circuit to be changed if the width differs from a standard associated with the tube whereby the scan rate is kept constant despite changes in the deflection sensitivity of the tube.
Filed: March 5, 1974 Issued: June 10, 1975 cited by: 2 | ||
copyright © 2007-2022 Edwin E Klingman
all rights reserved